达姆Information and Communication Engineering 的试题，欢迎解答。

benq51c

The following datapath is given:

[ 本帖最后由 benq51c 于 2006-5-24 14:30 编辑 ]

STROM

还是英文的......

benq51c

After the data input, the following results should be stored in the registers using the lowest possible number of clock cycles:

               if A>=B                                               if A<B
r1             A+C                                                     A+B
r2            A+B                                                      B+C
r3                the bigger number among A, B and C


For example, if C>B>A, the results would be:

r1      A+B
r2      B+C
r3      C


The control unit notifies that the correct results are loaded in the registers by setting the END signal to 1 during one clock cycle, and then back to 0.

(A) Show how many different addition operations can be performed in one clock cycle. Show also for each addition, which different conditions can be tested in a single clock cycle.

(B) Develop a statechart (Mealy Automat) for a control unit which - working together with the given datapath - guarantee the desired behaviour. Show also the necessary register transfers in the transitions. Use in your statechart only the registers r1, r2 and r3, the input vector IN and the signals START and END.
Notation Example:
r2>r1 / r1 <- r1 + r2

[ 本帖最后由 benq51c 于 2006-5-24 14:33 编辑 ]

benq51c

The datapath outputs r1, r2 and r3 are directly connected to the respective register outputs, and were ommited in Figure 1 for the sake of simplicity.
In START=0 the automat is in wait state. On START=1 the three 32-bit words A, B and C are input through IN, within the three following clock cycles. The procedure is shown in Figure 3.

benq51c

All the connections are 32-bit vectors, except for the control signals and the GT.
A control unit should be implemented and connected to the datapath as follows: